Will Physical Scalability Sabotage Performance Gains?
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The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will soon be impossible to maintain one global clock over the entire chip, and sending signals across a billion-transistor processor may require as many as 20 cycles.
IEEE members see full online issues at Computer, Vol. 30, No. 9, September 1997 pp. 37-39
Computer magazine by Institute of Electrical and Electronics Engineers, Inc